Infineon Launches New OptiMOS Source bottom power MOSFET

     High power density, excellent performance and ease of use are the key requirements of current power system design. To this end, Infineon Technology Co., Ltd. introduced a new generation of OptiMOS Source Down (SD) power MOSFET, which provides a practical solution to the design challenges in terminal applications. The power MOSFET is PQFN packaged, 3.3 x 3.3 mm2, and supports a wide voltage range from 25 V to 100 V. This packaging can achieve higher efficiency, higher power density and industry-leading thermal performance indicators, reduce BOM costs, and set a new industry benchmark in the performance of power MOSFETs. The device has a wide range of applications, including motor drive, SMPS for servers, telecommunications and OR ing, and battery management systems.

     Compared with the traditional Drain Down packaging, the latest source bottom packaging technology can make the device dimensions close to the bare chip. In addition, this innovative packaging technology can also reduce the loss and further enhance the overall performance of the device. Compared with the most advanced drain bottom packaging, the source bottom packaging can reduce RDS (on) by 30%. The main advantages that this technological innovation can bring to the system design include: reducing the overall size, changing from the SuperSO8 5 x 6 mm2 package to the PQFN 3.3 x 3.3 mm2 package, which can reduce the space occupation by about 65%, so that the available space can be used more effectively, thus improving the power density and system efficiency of the terminal system.

     In addition, in the source bottom package, heat is transferred to the PCB through the heat conduction pad, rather than through the internal lead bonding or copper tape design, to improve the heat dissipation effect. This also reduces the junction shell thermal resistance (RthJC) from 1.8K/W to 1.4K/W, with a drop of more than 20%, so that excellent thermal performance can be achieved. The two models introduced by Infineon currently have different board areas. They are SD standard gate pole layout and SD gate pole centered layout. In the standard gate layout, the position of the electrical connection remains unchanged, so that the standard drain bottom package can be simply and directly replaced with a new source bottom package; In the center gate layout package, the gate pin is moved to the center position to facilitate the parallel connection of multiple MOSFETs. Both models can optimize PCB layout, reduce parasitic effects, improve PCB loss, and are easy to use.